FPGA-based implementation of an ASK/FSK detector for railway signalling balises
| Main Author: | |
|---|---|
| Publication Date: | 2019 |
| Format: | Master thesis |
| Language: | eng |
| Source: | Repositórios Científicos de Acesso Aberto de Portugal (RCAAP) |
| Download full: | http://hdl.handle.net/10773/29909 |
Summary: | This dissertation is inserted in the telecommunications field, specifically railway signalling telecommunications systems. This project was proposed by CAF Signalling and aims at implementing the safety function to assure the interoperability of both Automatic Train Protection Systems (ATP) systems, ERTMS and KER. Namely, distinguish Eurobalises and KER type balises. Throughout the work the detector is modelled in Simulink and converted to VHDL code. The final step of this dissertation is the implementation on the FPGA of a robust balise type detector capable of detecting the balise type under ideal and non-ideal conditions. The performance of the detector was evaluated with real and test balise signals under ideal conditions, AWGN noise and pulsing noise. |
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FPGA-based implementation of an ASK/FSK detector for railway signalling balisesASKFSKModulation DetectorFPGAERTMSRailway SignallingThis dissertation is inserted in the telecommunications field, specifically railway signalling telecommunications systems. This project was proposed by CAF Signalling and aims at implementing the safety function to assure the interoperability of both Automatic Train Protection Systems (ATP) systems, ERTMS and KER. Namely, distinguish Eurobalises and KER type balises. Throughout the work the detector is modelled in Simulink and converted to VHDL code. The final step of this dissertation is the implementation on the FPGA of a robust balise type detector capable of detecting the balise type under ideal and non-ideal conditions. The performance of the detector was evaluated with real and test balise signals under ideal conditions, AWGN noise and pulsing noise.Esta dissertação insere-se na área de telecomunicações, mais concretamente nos sistemas de telecomunicações na sinalização ferroviária. O trabalho foi proposto pela empresa CAF Signalling e tem como objectivo a implementação de uma função de segurança que assegura a interoperabilidade entre sistemas de Proteção Automática de Comboios (ATP), ERTMS e KER, distinguindo entre Eurobalisas e balisas KER. Ao longo do trabalho o detector foi modelado em Simulink e convertido em código VHDL.A fase final da dissertação consiste na implementação em FPGA de um detetor de tipo de balisa capaz de operar em condições não ideais. O funcionamento do detector foi avaliado com sinais de teste e sinais reais em condições ideais, de ruído AWGN e ruído pulsante.2020-11-26T14:42:46Z2019-12-01T00:00:00Z2019-12info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/masterThesisapplication/pdfhttp://hdl.handle.net/10773/29909engMarques, Marcelo Rodrigo Almeidainfo:eu-repo/semantics/openAccessreponame:Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)instname:FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologiainstacron:RCAAP2024-05-06T04:28:51Zoai:ria.ua.pt:10773/29909Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireinfo@rcaap.ptopendoar:https://opendoar.ac.uk/repository/71602025-05-28T14:10:01.295673Repositórios Científicos de Acesso Aberto de Portugal (RCAAP) - FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologiafalse |
| dc.title.none.fl_str_mv |
FPGA-based implementation of an ASK/FSK detector for railway signalling balises |
| title |
FPGA-based implementation of an ASK/FSK detector for railway signalling balises |
| spellingShingle |
FPGA-based implementation of an ASK/FSK detector for railway signalling balises Marques, Marcelo Rodrigo Almeida ASK FSK Modulation Detector FPGA ERTMS Railway Signalling |
| title_short |
FPGA-based implementation of an ASK/FSK detector for railway signalling balises |
| title_full |
FPGA-based implementation of an ASK/FSK detector for railway signalling balises |
| title_fullStr |
FPGA-based implementation of an ASK/FSK detector for railway signalling balises |
| title_full_unstemmed |
FPGA-based implementation of an ASK/FSK detector for railway signalling balises |
| title_sort |
FPGA-based implementation of an ASK/FSK detector for railway signalling balises |
| author |
Marques, Marcelo Rodrigo Almeida |
| author_facet |
Marques, Marcelo Rodrigo Almeida |
| author_role |
author |
| dc.contributor.author.fl_str_mv |
Marques, Marcelo Rodrigo Almeida |
| dc.subject.por.fl_str_mv |
ASK FSK Modulation Detector FPGA ERTMS Railway Signalling |
| topic |
ASK FSK Modulation Detector FPGA ERTMS Railway Signalling |
| description |
This dissertation is inserted in the telecommunications field, specifically railway signalling telecommunications systems. This project was proposed by CAF Signalling and aims at implementing the safety function to assure the interoperability of both Automatic Train Protection Systems (ATP) systems, ERTMS and KER. Namely, distinguish Eurobalises and KER type balises. Throughout the work the detector is modelled in Simulink and converted to VHDL code. The final step of this dissertation is the implementation on the FPGA of a robust balise type detector capable of detecting the balise type under ideal and non-ideal conditions. The performance of the detector was evaluated with real and test balise signals under ideal conditions, AWGN noise and pulsing noise. |
| publishDate |
2019 |
| dc.date.none.fl_str_mv |
2019-12-01T00:00:00Z 2019-12 2020-11-26T14:42:46Z |
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info:eu-repo/semantics/publishedVersion |
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info:eu-repo/semantics/masterThesis |
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masterThesis |
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publishedVersion |
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http://hdl.handle.net/10773/29909 |
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http://hdl.handle.net/10773/29909 |
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eng |
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eng |
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openAccess |
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application/pdf |
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