A FAST Hardware Decoder Optimized for Template Features to Obtain Order Book Data in Low Latency - Oliveira, Caio César Soares (2022)
High-Frequency Trading (HFT) systems require high computational performance for real-time trading and data analysis. The FAST protocol, an extension of the FIX protocol, is one of the main patterns adopted by these systems. This work implements an open-source component in FPGA-based hardware to decode financial messages and output the necessary tags for order book updates. The component implements the FAST and FIX protocols versions adopted by the B3 Brazilian stock exchange. The proposed hardware decodes messages with an average latency of 0.72us, and average throughput of 1.4 millions FAST messages per second, representing a reduction of two orders of magnitude compared to the same implementation executed in a software processo.