Conjunto Universal de Circuitos Lógicos Quaternários Reversíveis - DIOGO ANACHE DE SOUZA (2021)
The synthesis of digital circuits in binary logic uses minimization techniques, such as Karnaugh maps and the algorithms Quine-McCluskey, Petrick and Espresso, to obtain an equivalent expression, but with fewer terms and operations, which implies a reduced use of logic gates. It is possible to utilize multi-valued logic (MVL) to transmit more information across the interconexions. Following the optimization idea, it is also possible to reduce the energy dissipation of these circuits through reversible logic gates, which allow a bijective mapping between input and output. This concept is based on Landauer's principle, which states that for each lost bit of information, K*T*ln2 Joules of energy are dissipated. In this work the quaternary algebra was approached, being proposed a minimization methodology for this domain, as well as the design of reversible logic gates.