Soft error mitigation in asynchronous networks on chip - Pontes, Julian José Hilgemberg (2012)
In advanced deep submicron technologies, the aggressive scaling of the clock to increasingly higher frequencies has now terminated. At the circuit top level, global clocking is not feasible anymore, which has led to the popularization of the Globally Asynchronous Locally Synchronous paradigm for constructing complex system on chip devices, with local islands of clocked logic interconnected by asynchronous communication. By providing packet-based communication and scalable communication parallelism compared to traditional bus-based communication, asynchronous network- on-chip have recently shown their benefits compared to their synchronous counterparts to build future many-core architectures, in terms of both performance and power. One of the next challenges for such asynchronous communication architectures is reliability, in the form of robustness to single event effects, when under the impact of particles generated by ionizing radiation. This occurs because technology downscaling continuously increases the logic sensitivity of silicon devices to such effects. Contrary to what happens in synchronous circuits, delay variations induced by radiation usually have no impact on asynchronous quasi-delay insensitive (QDI) combinational logic blocks, but in case of storage logic, bit flips may corrupt the circuit state with no recovery solution, even when using asynchronous circuits. This work proposes a new set of hardening techniques against single event effects applicable to asynchronous networks-on-chip. It presents practical case studies of use for these techniques and evaluates them in close to real life situations. The obtained results show that the achieved increase in asynchronous network-on-chip robustness has the potential to leverage this communication architecture solution as the main choice for the next generations of complex silicon devices on advanced nodes technologies such as 32 nm, 28 nm, 20 nm and below